This was a heads-down working week for Team FLASH. After presenting our PDR to other IPPD teams and our coach, we spent most of our time working through the feedback. Much of it pushed us toward the same thing, which was cutting detail that did not need to be there. Our first version tried to explain the entire chip design flow, and the clearer move is to go deep on the few areas our tooling actually touches and trust the audience on the rest. We rewrote several slides around that idea and tightened the design document to match.

We also started running scheduled practice presentations. Rehearsing out loud has caught problems that reading the slides did not, since a few sections that looked fine on the page turned out to be awkward to say and harder to follow than we thought. Getting reps in now means the version we present to our sponsor will be one we have already worked the rough edges out of.

Most of our week went into the Preliminary Design Review. Putting it together meant turning a broad statement of work into goals we can actually measure, which took longer than we expected. Our two main targets are catching and fixing most design rule check (DRC) violations automatically, and cutting the engineering hours that step currently takes.

We presented three concepts for the DRC engine. One predicts a fix from the violation itself, one looks up the relevant foundry rules and explains a proposed fix, and one proposes a change, reruns DRC, and adjusts based on what comes back. We are leaning toward the third, since it is the only one that checks whether its own suggestion worked.

In our liaison meeting we decided to focus on the digital flow rather than analog, which narrows our scope enough to go deeper.

Several members of Team FLASH attended a White Belt Quality Workshop hosted by IPPD this week, presented by Florida Power & Light and led by Linda Linnus and Dr. Doreen Ayafor. The workshop introduced Lean Six Sigma concepts including the DMAIC framework (Define, Measure, Analyze, Improve, Control), process mapping, root cause analysis, and how to measure whether a change actually improved anything. The most useful part for our project was the emphasis on defining the problem before jumping to a solution, and on picking a baseline metric up front so improvement can be proven rather than assumed. That maps directly onto what we are building. Our goal is to reduce the manual iteration engineers spend inside the Synopsys design flow, and we will only know whether our AI tooling helps if we measure the current process first. We also presented our draft ASIC flow diagram to our liaisons and updated it based on their feedback, since Synopsys Fusion Compiler now combines the synthesis and place-and-route steps we had drawn separately. For AI integration, the team is leaning toward an agentic approach that breaks a goal into sub-tasks on its own while keeping the engineer in control of the decisions, rather than either a fully manual prompt-by-prompt tool or a fully autonomous one.

This week our team moved from planning into a hands-on setup. We confirmed access to the Synopsys tool suite on UF’s ECE Linux servers, checked out our first Design Compiler license, and loaded the SAED 32/28nm educational library as a practice target. To give everyone on the team the same picture of how a chip gets built, we mapped out the full digital ASIC flow shown below, from RTL and synthesis through place-and-route and signoff. This map is helping us identify where AI assistance could save engineers the most time, and design-rule-check (DRC) cleanup is standing out as an early target. At Thursday’s meeting, our Lockheed Martin liaisons approved the FLASH name and logo, and we began planning our site visit to Lockheed Martin Orlando in early October. Next week we plan to push a small test design through synthesis and keep gathering the reference documentation we need. 

This week we met with both our coach, Dr. Rickard Ewetz, and our Lockheed Martin liaison engineer, Andrew Stebbins and GregZ Cieslewski. Dr. Ewetz helped us review expectations and organize how we’re setting up responsibilities and recurring meetings, while our liaison meetings let us iron out the main goals and objectives of the project and gain deeper clarity on the technical direction, tools, and workflow. We also aligned on our next steps so we can start moving from planning toward real development. 

We’ve already begun meeting weekly and came up with a team name and logo, FLASH, which represents our project and our values. 

Hello everyone, and welcome to our team’s blog! This year we’re partnering with Lockheed Martin on a project in AI-assisted chip design. Our goal is to build AI tools that help engineers design custom chips (ASICs) faster and with fewer manual iterations, working inside the industry-standard Synopsys design flow. Throughout the year we’ll use this page to document our journey, progress, and milestones. 

Looking ahead, we’ll be working on getting our development environment and tool access set up and mapping out how we’ll approach the design flow. 

Our team members: 

• Andrew Fesenko 

• Ariana Delamata 

• Cesar Valentin 

• Miguel Sanchez 

• Monica Harrell 

• Jason He